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cat5259 ? catalyst semiconductor, inc. 1 doc. no. md-2000 rev. h characteristics subject to change without notice nonvolatile data registers control logic wiper control registers i2c bus interface r w 0 r w1 r w 2 r w 3 r l0 a 0 a 1 scl sda a 2 a 3 r l1 r l2 r l3 r h0 r h1 r h2 r h3 wp quad digitally programmable potentiometers (dpp?) with 256 taps and i2c interface features ? four linear taper digitally programmable potentiometers ? 256 resistor taps per potentiometer ? end to end resistance 50k ? or 100k ? ? potentiometer control and memory access via i2c interface ? low wiper resistance, typically 100 ? ? nonvolatile memory storage for up to four wiper settings for each potentiometer ? automatic recall of saved wiper settings at power up ? 2.5 to 6.0 volt operation ? standby current less than 1a ? 1,000,000 nonvolatile write cycles ? 100 year nonvolatile memory data retention ? 24-lead soic and 24-lead tssop packages ? industrial temperature range for ordering information details, see page 15. pin configuration soic (w) tssop (y) nc 1 24 a3 a0 2 23 scl r w3 3 22 r l2 r h3 4 21 r h2 r l3 5 20 r w2 nc 6 19 nc v cc 7 18 gnd r lo 8 17 r w1 r ho 9 16 r h1 r wo 10 15 r l1 a2 11 14 a1 12 13 sda description the cat5259 is four digitally programmable poten? tiometers (dpps?) integrated with control logic and 16 bytes of nvram memory. each dpp consists of a series of resistive elem ents connected between two externally accessible end points. the tap points between each resistive elem ent are connected to the wiper outputs with cmos switches. a separate 8-bit control register (wcr) independently controls the wiper tap switches for each dpp. associated with each wiper control register are four 8-bit non-volatile memory data registers (dr) used for storing up to four wiper settings. writing to t he wiper control register or any of the non-volatile data registers is via a i2c serial bus. on power-up, the contents of the first data register (dr0) for each of the four potentiometers is automatically loaded into its respective wiper control registers. the cat5259 can be used as a potentiometer or as a two terminal, variable resistor. it is intended for circuit level or system level adjustments in a wide variety of applications. it is available in the 0oc to 70oc commercial and -40oc to 85oc industrial operating temperature ranges and offered in a 24-lead soic and tssop package. functional diagram
cat5259 doc. no. md-2000 rev. h 2 ? catalyst semiconductor, inc. characteristics subject to change without notice pin descriptions scl: serial clock the cat5259 serial clock input pin is used to clock all data transfers into or out of the device. sda: serial data the cat5259 bidirectional serial data pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-ored with the other open drain or open collector i/os. a0, a1, a2, a3: device address inputs these inputs set the device address when addressing multiple devices. a total of sixteen devices can be addressed on a single bus. a match in the slave address must be made with the address input in order to initiate communication with the cat5259. r h , r l : resistor end points the four sets of r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. r w : wiper the four r w pins are equivalent to the wiper terminal of a mechanical potentiometer. wp : write protect input the wp pin when tied low prevents non-volatile writes to the device (change of wiper control register is allowed) and when tied high or left floating normal read/write operations are allowed. see write protection on page 6 for more details. device operation the cat5259 is four resistor arrays in tegrated with a i2c serial interface l ogic, four 8-bit wiper control registers and sixteen 8-bit, non-volatile memory data registers. ea ch resistor array contains 255 separate resistive elements connected in series. the physical ends of eac h array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). the tap positions between and at the ends of the series resistors are connected to the output wiper terminals (r w ) by a cmos transistor switch. only one tap point for each potentiometer is connected to its wiper terminal at a ti me and is determined by the value of the wiper control register. data can be read or written to the wiper contro l registers or the non-volatile memory data registers via the i2c bus. additional instructions allow data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. also, the device can be instructed to operate in an "increment/decrement" mode. pin # name function 1 nc no connect 2 a0 device address, lsb 3 r w3 wiper terminal for potentiometer 3 4 r h3 high reference terminal for potentiometer 3 5 r l3 low reference terminal for potentiometer 3 6 nc no connect 7 v cc supply voltage 8 r l0 low reference terminal for potentiometer 0 9 r h0 high reference terminal for potentiometer 0 10 r w0 wiper terminal for potentiometer 0 11 a2 device address 12 wp write protection 13 sda serial data input/output 14 a1 device address 15 r l1 low reference terminal for potentiometer 1 16 r h1 high reference terminal for potentiometer 1 17 r w1 wiper terminal for potentiometer 1 18 gnd ground 19 nc no connect 20 r w2 wiper terminal for potentiometer 2 21 r h2 high reference terminal for potentiometer 2 22 r l2 low reference terminal for potentiometer 2 23 scl bus serial clock 24 a3 device address
cat5259 ? catalyst semiconductor, inc. 3 doc. no. md-2000 rev. h characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units temperature under bias -55 to +125 oc storage temperature -65 to +150 c voltage on any pin with respect to v ss (1) (2) -2.0 to +v cc + 2.0 v v cc with respect to ground -2.0 to +7.0 v package power dissipation capability (t a = 25oc) 1.0 w lead soldering temperature (10sec) 300 oc wiper current 6 ma recommended operating conditions parameters ratings units v cc +2.5 to +6 v industrial temperature -40 to +85 c potentiometer characteristics (over recommended operating conditions unless otherwise stated.) limits symbol parameter test conditions min typ. max. units r pot potentiometer resistance (100k ? ) 100 k ? r pot potentiometer resistance (50k ? ) 50 k ? potentiometer resistance tolerance 20 % r pot matching 1 % power rating 25c, each pot 50 mw i w wiper current +3 ma r w wiper resistance i w = 3ma @ v cc = 3v 200 300 ? r w wiper resistance i w = 3ma @ v cc = 5v 100 150 ? v term voltage on any r h or r l pin v ss = 0v v ss v cc v v n noise (4) nv hz resolution 0.4 % absolute linearity (5) r w(n)(actual) -r (n)(expected) (8) 1 lsb (7) relative linearity (6) r w(n+1) -[r w(n)+lsb ] (8) 0.2 lsb (7) tc rpot temperature coefficient of r pot (4) 300 ppm/oc tc ratio ratiometric temp. coefficient (4) 20 ppm/oc c h /c l /c w potentiometer capacitances (4) 10/10/25 pf fc frequency response r pot = 50k ? (4) 0.4 mhz notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the minimum dc input voltage is ?0.5v. during transitions, inputs may undershoot to ?2.0v for periods of less than 20ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20ns. (3) latch-up protection is provided for stresses up to 100ma on address and data pins from ?1v to v cc +1v. (4) this parameter is tested initially and after a design or process change that affects the parameter. (5) absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position wh en used as a potentiometer. (6) relative linearity is utilized to determine the actual c hange in voltage between two successive tap positions when used as a potentio- meter. it is a measure of the error in step size. (7) lsb = r tot / 255 or (r h - r l ) / 255, single pot (8) n = 0, 1, 2, ..., 255
cat5259 doc. no. md-2000 rev. h 4 ? catalyst semiconductor, inc. characteristics subject to change without notice d.c. operating characteristics v cc = +2.5v to +6.0v, unless otherwise specified. symbol parameter test conditions min max units i cc1 power supply current f scl = 400khz, sda = open v cc = 6v, inputs = gnd 1 ma i cc2 power supply current non-volatile write f sck = 400khz, sda open v cc = 6v, input = gnd 5 ma i sb standby current (v cc = 5.0v) v in = gnd or v cc , sda = open 5 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage -1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3.0v) i ol = 3 ma 0.4 v capacitance t a = 25oc, f = 1.0mhz, v cc = 5v symbol test conditions max. units c i/o (1) input/output capacitance (sda) v i/o = 0v 8 pf c in (1) input capacitance (a0, a1, a2, a3, scl, wp ) v in = 0v 6 pf a.c. characteristics 2.5v - 6.0v symbol parameter min. max. units f scl clock frequency 400 khz t i (1) noise suppression time constant at scl, sda inputs 200 ns t aa slc low to sda data out and ack out 1 s t buf (1) time the bus must be free before a new transmission can start 1.2 s t hd:sta start condition hold time 0.6 s t low clock low period 1.2 s t high clock high period 0.6 s t su:sta start condition setuptime (for a repeated start condition) 0.6 s t hd:dat data in hold time 0 ns t su:dat data in setup time 50 ns t r (1) sda and scl rise time 0.3 s t f (1) sda and scl fall time 300 ns t su:sto stop condition setup time 0.6 s t dh data out hold time 100 ns notes: (1) this parameter is tested initially and after a des ign or process change that affects the parameter.
cat5259 ? catalyst semiconductor, inc. 5 doc. no. md-2000 rev. h characteristics subject to change without notice power up timing (1)(2) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms wiper timing symbol parameter min max units t wrpo wiper response time after power supply stable 5 10 s t wrl wiper response time after instruction issued 5 10 s write cycle limits (3) symbol parameter max units t wr write cycle time 5 ms reliability characteristics symbol parameter reference test method min max units n end (4) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (4) data retention mil-std-883, test method 1008 100 years v zap (4) esd susceptibility mil-std-883, test method 3015 2000 v i lth (4) latch-up jedec standard 17 100 ma figure 1. bus timing notes: (1) this parameter is tested initially and after a des ign or process change that affects the parameter. (2) t pur and t puw are delays required from the time v cc is stable until the specified operation can be initiated. (3) the write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are di sabled, sda is allowed to remain high, and the device does not respond to its slave add ress. (4) this parameter is tested initially and after a design or process change that affects the parameter. t high scl sda in s d aout t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat5259 doc. no. md-2000 rev. h 6 ? catalyst semiconductor, inc. characteristics subject to change without notice serial bus protocol the following defines the features of the i2c bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the cat5259 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat5259 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 0101 for the cat5259 (see figure 5). the next four significant bits (a3, a2, a1, a0) are the device address bits and define which device the master is accessing. up to sixteen devices may be individually addressed by the system. typically, +5v and ground are hard-wired to these pins to establish the device's address. after the master sends a start condition and the slave address byte, the cat5259 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signa ling that it received the 8 bits of data. the cat5259 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat5259 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat5259 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations in the write mode, the master device sends the start condition and the slave address information to the slave device. after the slave generates an acknowledge, the master se nds the instruction byte that defines the requested operation of cat5259. the instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. after receiving another acknowledge from the slave, the master device transmits the data to be written into the selected register. the cat5259 acknowledges once more and the master generates the stop condition, at which time if a non-volatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the cat5259 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave addres s. if the cat5259 is still busy with the write operation, no ack will be returned. if the cat5259 has completed the write operation, an ack will be returned and the host can then proceed with the next instruction operation. write protection the write protection feature allows the user to protect against inadvertent programming of the non-volatile data registers. if the wp pin is tied to low, the data registers are protected and become read only. similarly, the wp pin is going low after start will interrupt non-volatile write to data registers, while wp pin going low after an internal write cycle has started will have no effect on any write operation. the cat5259 will accept both slave addresses and instructions, but the data registers are protected from programming by the device?s failure to send an acknowledge after data is received.
cat5259 ? catalyst semiconductor, inc. 7 doc. no. md-2000 rev. h characteristics subject to change without notice figure 2. write cycle timing figure 3. start/stop condition figure 4. acknowledge condition figure 5. slave address bits cat5259 0 1 0 1 a3 a2 a1 a0 * a0, a1, a2 and a3 correspond to pin a0, a1, a2 and a3 of the device. ** a0, a1, a2 and a3 must compare to its corresponding hard wired input pins. t wr stop condition start condition address ack 8th bit byte n scl sda start condition sda stop condition scl acknowledge 1 start scl from master 89 data output from transmitter data output from receiver
cat5259 doc. no. md-2000 rev. h 8 ? catalyst semiconductor, inc. characteristics subject to change without notice instruction and register description slave address byte the first byte sent to the cat5259 from the master/processor is called the slave/dpp address byte. the most significant four bits of the slave address are a device type ident ifier. these bits for the cat5259 are fixed at 0101[b] (refer to table 1). the next four bits, a3 - a0, are the internal slave address and must match the physical device address which is defined by the state of the a3 - a0 input pins for the cat5259 to successfully continue the command sequence. only the device which slave address matches the incomi ng device address sent by the master executes the instruction. the a3 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . instruction byte the next byte sent to the cat5259 contains the instruction and register poin ter information. the four most significant bits used provide the instruction opcode i3 - i0. the r1 and r0 bits point to one of the four data registers of ea ch associated potentiometer. the least two significant bits point to one of four wiper control registers. the format is shown in table 2. data register selection data register selected r1 r0 dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 figure 6. write timing table 1. identification byte format table 2. instruction byte format s a c k a c k dr1 wcrdata s t o p p bus activity: master sda line s t a r t a c k slave/dpp address instruction byte fixed variable op code register address pot1 wcr address id3 id2 id1 id0 a3 a2 a1 a0 0101 ( msb ) ( lsb ) device type identifier slave address i3 i2 i1 i0 r1 r0 p1 p0 (msb) (lsb) instruction data register wcr/pot selection opcode selection
cat5259 ? catalyst semiconductor, inc. 9 doc. no. md-2000 rev. h characteristics subject to change without notice wiper control and data registers wiper control register (wcr) the cat5259 contains four 8-bit wiper control registers, one for each potentiometer. the wiper control register output is decoded to select one of 256 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written by the host via writ e wiper control register instruction; it may be written by transferring the contents of one of four associated data registers via the xfr data register instruction, it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the content of its data register zero (dr0) upon power-up. the wiper control register is a volatile register that loses its contents when the cat5259 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers (dr) each potentiometer has four 8-bit non-volatile data registers. these can be read or written directly by the host. data can also be tran sferred between any of the four data registers and the associated wiper control register. any data changes in one of the data registers is a non-volatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as standard memory locations for system parameters or user preference data. instructions four of the nine instructions are three bytes in length. these instructions are: ? read wiper control register ? read the current wiper position of the selected potentiometer in the wcr ? write wiper control register ? change current wiper position in the wcr of the selected potentiometer ? read data register ? read the contents of the selected data register ? write data register ? write a new value to the selected data register the basic sequence of the three byte instructions is illustrated in figure 8. thes e three-byte instructions table 3. instruction set instruction set instruction i3 i2 i1 i0 r1 r0 wcr1/p1 wcr0/p0 operation read wiper control register 1 0 0 1 0 0 1/0 1/0 read the contents of the wiper control register pointed to by p1-p0 write wiper control register 1 0 1 0 0 0 1/0 1/0 write new value to the wiper control register pointed to by p1-p0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the data register pointed to by p1-p0 and r1-r0 write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the data register pointed to by p1-p0 and r1-r0 xfr data register to wiper control register 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the data register pointed to by p1-p0 and r1-r0 to its associated wiper control register xfr wiper control register to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wiper control register pointed to by p1-p0 to the data register pointed to by r1-r0 gang xfr data registers to wiper control registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by r1-r0 of all four pots to their respective wiper control registers gang xfr wiper control registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper control registers to their respective data registers pointed to by r1-r0 of all four pots increment/decrement wiper control register 0 0 1 0 0 0 1/0 1/0 enable increment/decrement of the control latch pointed to by p1-p0 note: 1/0 = data is one or zero.
cat5259 doc. no. md-2000 rev. h 10 ? catalyst semiconductor, inc. characteristics subject to change without notice exchange data between the wcr and one of the data registers. the wcr controls the position of the wiper. the response of the wiper to this action will be delayed by t wr . a transfer from the wcr (current wiper position), to a data register is a write to non- volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. four instructions require a two-byte sequence to complete, as illustrated in fi gure 7. these instructions transfer data between the host/processor and the cat5259; either between t he host and one of the data registers or directly bet ween the host and the wiper control register. these instructions are: ? xfr data register to wiper control register this transfers the contents of one specified dataregister to the associated wiper control register. ? xfr wiper control register to data register this transfers the contents of the specified wiper control register to the specified associated data register. ? gang xfr data register to wiper control register this transfers the contents of all specified data registers to the associated wiper control registers. ? gang xfr wiper counter register to data register this transfers the conten ts of all wiper control registers to the specified associated data registers. increment/decr ement command the final command is increment/decrement (figure 9 and 10). the increment/decrement command is different from the other commands. once the command is issued and the cat5259 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tu ning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while sda is low, t he selected wiper will move one resistor segment towards the rl terminal. see instructions format for more detail. figure 7. two-byte instruction sequence figure 8. three-byte instruction sequence figure 9. increment/decrement instruction sequence s t a r t 0101 a2 a0 a c k i2 i1 i0 r1 r0 p1 a c k sda s t o p id3 id2 id1 id0 p0 device id internal instruction opcode address register address pot/wcr address a1 a3 i3 i3 i2 i1 i0 r1 r0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address wcr[7:0] or data register d[7:0] s t a r t 0101 a2 a1 a0 a c k p1 p0 a c k sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 a3 i3 i2 i1 i0 id3 id2 id1 id0 device id internal instruction opcode address data register address pot/wcr address s t a r t 0101 a2 a1 a0 a c k r0 p1 p0 a c k sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n r1 a3
cat5259 ? catalyst semiconductor, inc. 11 doc. no. md-2000 rev. h characteristics subject to change without notice figure 10. increment/decrement timing limits instruction format read wiper control register (wcr) device addresses instruction data 0 1 0 1 a a a a 1 0 0 1 00pp 76543210 s t a r t 3 2 1 0 a c k 10 a c k a c k s t o p write wiper control register (wcr) device addresses instruction data 0 1 0 1 a a a a 1 0 1 0 00pp 76543210 s t a r t 3 2 1 0 a c k 10 a c k a c k s t o p read data register (dr) device addresses instruction data 0 1 0 1 a a a a 1 0 1 1 rrpp 76543210 s t a r t 3 2 1 0 a c k 1010 a c k a c k s t o p write data register (dr) device addresses instruction data 0 1 0 1 a a a a 1 1 0 0 rrpp 76543210 s t a r t 3 2 1 0 a c k 1010 a c k a c k s t o p scl sda r w inc/dec command issued voltage out t wrl
cat5259 doc. no. md-2000 rev. h 12 ? catalyst semiconductor, inc. characteristics subject to change without notice instruction format (continued) gang transfer data register (dr) to wiper control register (wcr) device addresses instruction 0 1 0 1 a a a a 0 0 0 1 r r 0 0 s t a r t 3 2 1 0 a c k 10 a c k s t o p gang transfer wiper control register (wcr) to data register (dr) device addresses instruction 0 1 0 1 a a a a 1 0 0 0 r r 0 0 s t a r t 3 2 1 0 a c k 10 a c k s t o p transfer wiper control register (wcr) to data register (dr) device addresses instruction 0 1 0 1 a a a a 1 1 1 0 r r p p s t a r t 3 2 1 0 a c k 1010 a c k s t o p transfer data register (dr) to wiper control register (wcr) device addresses instruction 0 1 0 1 a a a a 1 1 0 1 r r p p s t a r t 3 2 1 0 a c k 1010 a c k s t o p increment (i)/decrement (d) wi per control register (wcr) device addresses instruction data 0 1 0 1 a a a a 0 0 1 0 0 0 p p s t a r t 3 2 1 0 a c k 10 a c k i \ d i \ d . . . i \ d i \ d s t o p note: (1) any write or transfer to the non-volatile data registers is followed by a high voltage cycle after a stop has been issued.
cat5259 ? catalyst semiconductor, inc. 13 doc. no. md-2000 rev. h characteristics subject to change without notice package outline drawings soic 24-lead 300mils (w) (1)(2) notes: (1) all dimensions in millimeters. angle in degrees. (2) compiles with jedec standard ms-013. e1 e a1 a2 e pin#1 identification b d c a top view side view end view 1 1 h h l symbol min nom max a2.35 2.65 a1 0.10 0.30 a2 2.05 2.55 b0.31 0.51 c0.20 0.33 d 15.20 15.40 e 10.11 10.51 e1 7.34 7.60 e 1.27 bsc h0.25 0.75 l0.40 1.27 0 8 1 5 15
cat5259 doc. no. md-2000 rev. h 14 ? catalyst semiconductor, inc. characteristics subject to change without notice tssop 24-lead 4.4mm (y) (1)(2) notes: (1) all dimensions in millimeters. angle in degrees. (2) compiles with jedec standard ms-153. for current tape and reel information, download the pdf file from: htt p ://www.catsemi.com/documents/ta p eandreel. p df. 1 a 1 a2 d top view side view end view e e1 e b l1 c l a symbol min nom max a1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.80 7.90 e 6.25 6.40 6.55 e1 4.30 4.40 4.50 e 0.65 bsc l 1.00 ref l1 0.50 0.60 0.70 10 8
cat5259 ? catalyst semiconductor, inc. 15 doc. no. md-2000 rev. h characteristics subject to change without notice example of ordering information (1) ordering part number part number resistance package cat5259wi-50 50k ? cat5259wi-00 100k ? soic cat5259yi-50 50k ? CAT5259YI-00 100k ? tssop notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead finish is matte-tin. (3) the device used in the above example is a cat5259wi-00-t1 (soic, industrial temperature, 100k ? , tape & reel, 1,000/reel). (4) for additional package and temperature options, please contact your nearest ca talyst semiconductor sales office prefix device # suffix cat 5259 w i -00 - t1 company id package w: soic y: tssop temperature range i = industrial (-40oc to 85oc) product numbe r 5259 resistance 50: 50k ? 00: 100k ? tape & reel t: tape & reel 1: 1,000/reel - soic 2: 2,000/reel - tssop
revision history date rev. reason 11/12/04 c eliminated bga package in all areas eliminated commercial temperature range added ?green? pack age marking 03/18/04 d added tssop package in all areas 05/07/04 e updated functional diagram updated pin descriptions updated notes in absolute max. ratings updated potentiometer characteristics table updated dc characteristics table added wiper table updated write protection text changed figure 3 drawing to start/stop condition from start/stop timing changed figure 4 title from acknowledge timing to acknowledge condition corrected instruction format for gang transfer data register (dr) to wiper control register (wcr) 09/21/04 f updated dc operat ing characteristics table 01/23/08 g updated example of ordering information updated package outline drawings added md- to document number 04/08/08 h change 2-wire with i2c update ordering part number table catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: md-2000 fax: 408.542.1200 revision: h www.catsemi.com issue date: 04 / 08 / 08 copyrights, trademarks and patents ? catalyst semiconductor, inc. trademarks and register ed trademarks of catalyst semiconductor include each of the following: adaptive analog?, beyond memory?, dpp?, ezdim?, ldd?, minipot?, quad-mode? and quant um charge programmable? i 2 c? is a trademark of philips corporati on. catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or guar antee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any produ ct or service descr ibed herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete.

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